(1) Field of the Invention
The invention relates to a switched-capacitor multiplier circuit for multiplying an information signal x(t) by a periodical bipolar carrier signal d(t). A multiplier circuit of this type can be used, for example, as an amplitude demodulator in a stereodecoder (see, for example, reference 1), but also as a phase detector in a phase-locked loop (see, for example, reference 3).
(2) Description of the Prior Art
Multiplier circuits of this type have extensively been described in, for example, references 1, 2 and 3. They generally comprise a distributed multiplier circuit and a control pulse circuit. The latter supplies control pulses at a rate of, for example, f.sub.s. The distributed multiplier circuit is formed by a plurality of signal channels each receiving the information signal x(t) and being provided with a cascade arrangement of a switching circuit and a weighting network having a given positive or negative weighting factor. These switching circuits are controlled in a predetermined sequence by the sequence of control pulses so that at least during a given period (for example, the duration of a control pulse) the information signal is applied to the weighting network. In this manner each signal channel supplies an output signal and all these output signals are summed in an adder.
The required weighting factors are obtained by sampling the carrier signal d(t) with the previously mentioned frequency f.sub.s which is to be chosen in such a manner that a series of N periodically recurring carrier signal samples d.sub.1, d.sub.2, d.sub.3, . . . , d.sub.N is obtained. The number of signal channels (including those having a weighting factor which is possibly equal to zero) is then in principle taken to be equal to N. When the k-th carrier signal sample is indicated by d.sub.k (where k=1, 2, 3, . . . , N) the weighting factor in the k-th signal channel is equal to d.sub.k.
Since this multiplier circuit is of the switched-capacitor type, each weighting network includes a capacitor, and the adder is constituted by an operational amplifier bridged by a capacitor having a capacitance C. The capacitance of the capacitor in the k-th signal channel will be indicated by C(k) for which principally applies that: EQU C(k)=.vertline.d.sub.k .vertline..multidot.C
where .vertline.d.sub.k .vertline. represents the magnitude of the carrier signal sample d.sub.k.
If the series of carrier signal samples consists exclusively of positive carrier signal samples (definitely positive), the implementation of the multiplier circuit follows directly from the foregoing. However, if several carrier signal samples from the series are negative, so that also negative weighting factors are to to realized, a number of further steps will have to be taken. The simplest step is the one in which the information signal is applied via a polarity inverter circuit to the switching circuit in each signal channel in which a negative weighting factor is to be realised (see, for example, FIG. 6 in reference 3). A further possibility is to provide the distributed multiplier circuit with a chopper circuit through which the information signal is applied to the signal channels. This chopper circuit applies the information signal in an unchanged form to the signal channels if the instantaneous value of the information signal is to be multiplied by a positive carrier signal sample. If this multiplication is, however, to be effected with a negative carrier signal sample, the information signal is inverted in polarity by the chopper circuit. Characteristic of all the above-mentioned cases is that a product signal is obtained at the output of the adder which signal is equal to the product of the information signal x(t) and the periodical bipolar carrier signal d(t). It appears from the foregoing that the carrier signal d(t) is not present in an explicitly time-continuous form. This will hereinafter become manifest by the phase "a given multiplier sigal is associated with the distributed multiplier circuit"; the carrier signal d(t) in the cases described hereinbefore.
The switched-capacitor multiplier circuits formed in this manner frequently exhibit an unwanted offset voltage at the output of the adder, which voltage is generated by the distributed multiplier circuit itself. It is generally built up of two components. The first component is supplied by the operational amplifier in the adder; the op-amp offset. The second component is supplied by the switching circuits, more particularly by the parasitic capacitances in these switching circuits and is generally referred to as clock feed-through. Both components arise independently of each other, but they are often inadmissibly high. When using this multiplier circuit in, for example, a stereodecoder circuit, this offset voltage should be less than 2 mV to achieve a channel separation of more than 50 dB. It is found that this cannot be realised in practice without special steps.